1. Field of the Invention
This invention relates to logic and array system testing and, more particularly, to the level sensitive testing of functional organizations of a logic array system utilized in digital computers and the like.
2. Description of the Prior Art
In the past, the designer of computer logic has had complete flexibility in arranging logic circuitry and arrays to implement system and sub-system logic functions in central processing units, channels and control units employed in digital computing apparatus and the like. A significant variety of design implementations has resulted from the exercise of this flexibility. Each of these implementations has its own special dependency on the characteristics of the individual circuits employed in the system. The interface that existed between the logic designer and component manufacturer as a result of these implementations was reasonably well defined and the approach of the past could be supported in component manufacturing since the parameters of the circuits could rather readily be tested.
With the advent of large scale integration, however, this well defined and reliably tested interface no longer exists. Large scale integration, as is well known, provides the ability for the logic designer as well as the component manufacturer, to maximize the capacity for placing hundreds of circuits on a single chip of semiconductive material or a complete array on a single chip. Such an ability offers the potential for reducing power, increasing speed, and significantly reducing the cost of digital circuits. However, with such highly dense configurations, it is impossible or impractical to test each circuit or array for all of the well known circuit parameters. As a result, it is necessary to partition and divide logic and array systems and subsystems into functional units having characteristics that are substantially insensitive to these individual parameters. A generalized and modular logic system with embedded arrays, of this type is described in application Ser. No. 701,052 entitled "Level Sensitive Embedded Array Logic System" filed June 30, 1976 by Messrs E. B. Eichelberger, E. I. Muehldorf, R. G. Walther and T. W. Williams and assigned to the same assignee. Such functional units require testing methods that measure the performance of the entire functional package. The testing methods of the past are unable to determine the performance of such functional units.
In the past, for example, each individual circuit and array has been tested for the usual and normal ac and dc parameters. Access to the modular unit for applying the input test conditions and measuring the output responses has been achieved through a fixed number of input/output connection pins. However, in the realm of large scale integrated functional units, the same number of input/output pins are available, but there is considerably more circuitry and arrays.
Thus, in a typical module containing 100 chips with logic chips having up to six hundred circuits (averaging 400 circuits) and 25 array chips, the module would contain at least 30,000 circuits and 25 array chips. Parametric tests cannot be performed on individual circuit units. Accordingly, the testing must be performed on an entire functional logic unit, be it at the chip level, the modular level, or other level.
As is known, the functional units of a logic system are formed of combinational logic, and arrays as well as sequential circuits. Although computational procedures are available for computing tests and test patterns for combinational circuits, such procedures are exceedingly difficult to apply for sequential circuits with arrays and no general solution has yet been found to the problem of generating test patterns for complicated sequential logic circuits. These latter circuits are dependent on their prior history as well as any test patterns that are applied to them, consequently, it is necessary that all sequential circuitry in a logic system be effectively reduced to combinational circuitry to effectuate a test procedure on a network of circuits. The aforecited application describes logic circuitry capable of effectively rendering the circuitry combinational plus array in form. Automatic test pattern generation may then be utilized in providing test patterns for the entire logic system.